The present invention is an analog to digital converter for converting an analog charge based signal to a digital representation of the analog signal.
Conventional low-speed analog to digital converters operate by comparing a sampled analog voltage to a reference voltage, and adjusting the reference voltage until a null output is obtained. The digital device used to adjust the reference voltage is then decoded and read out as the digital equivalent. The reference voltage source used requires ultra-precision resistors, and dissipates power.
A typical successive-approximation analog to digital converter (A/D) is shown in block diagram form in FIG. 1. The input signal, usually held at a fixed level by a sample and hold circuit 31, is compared against the output of a digital to analog converter (D/A) 33. This is accomplished by inputting the sample and hold output and the D/A output into a differencing amplifier 35 and the amplifier output into a comparator 37.
At sample input time, the serial shift register and the bit latch 39 are set to all "0" by the control logic 41. The clock then advances the control logic at a fixed rate. The control logic shifts a "1" through the serial shift register. The control logic also, in combination with the comparator, sets the bit latch. The output from the shift register is ORed with the bit latch to control the D/A converter.
The A/D converter is exercised starting with the Most 10 Significant Bit (MSB). The MSB is activated in the D/A by the 11 shift register, causing comparison of the input against a 1/2 of full scale value. If the differencing amplifier output to the comparator indicates that the held input sample is more than 1/2 of full scale, as shown by the comparator 37, the MSB is left "ON", and a "1" is recorded in the bit latch for the MSB. If the differencing amplifier output to the comparator indicates that the input sample is less than 1/2 of full scale, the MSB is turned "OFF", and a "0" is recorded in the bit latch for the MSB.
The exercising of the A/D continues in order of descending bit weight, each bit weight being equal to 1/2 of the previous bit. Each bit weight is individually compared to the input sample via the D/A by summation with the D/A's output of the previous bits, if they were left "ON". The comparator therefore must be able to resolve a difference equal to the least significant bit.
FIG. 2 shows the bit weighting scheme of the typical A/D converters. The analog input signal is almost 3/4 of full scale. The MSB test produced a "1" for greater than half. This caused the D/A to be left "ON" for the MSB. The second bit equal to a 1/4 caused overflow and was set to "0" causing the D/A to be turned off for that bit. The third bit equal to 1/8 produced a "1" for a D/A sum less than the input so the D/A was left on. The fourth bit equal to a 1/16 caused overflow and was set to "0". causing the D/A to be turned off for that bit. The fifth bit equal to 1/32 produced a "1" for a D/A sum less than the input so the D/A was left "ON". The resultant output binary code was therefore 10101. The digital result can be serially output as each bit is evaluated or parallel output from the stored results. Accuracy, linearity, and speed are primarily affected by the properties of the D/A converter and the comparator.
The invention is particularly suited to converting the analog signals received from individual infrared detectors of a focal plane array to a digital form for processing by digital signal processing electronics. In that application, the output of a detector is an analog charge domain signal. This signal is sampled to produce a charge packet. Conventional voltage based analog to digital converters require that the charge packet analog signal be converted to a voltage prior to being input to the analog to digital converter. The charge packet to voltage conversion process is non-linear, and the voltage must be corrected following conversion.
Furthermore, in the infrared detector application, the signal processing electronics, including any charge to voltage and analog to digital converters, are frequently placed adjacent the detector array. Therefore, heat generated in the conversion processes may be transferred to the detectors, interfering with their operation.
The invention is also generally suitable for use with signals produced by charge coupled devices (CCD's) or other sources of charge domain signals.
The invention is further suitable for use with a voltage input, as the conversion from voltage to charge can be made quite linear.